The present invention concerns clock distribution circuits and techniques, particularly circuits and techniques related to reducing jitter in mixed-signal communications circuits, such as high-speed transmitters and receivers.
In the computer and telecommunications industries, many electronic devices are coupled together to operate as systems. For example, computers are often connected to printers, scanners, cameras, and even other computers. In such systems, a common occurrence is the communication of data between two devices: a sending device and a receiving device.
The sending device generally has the data in the initial form of a set of digital words (sets of ones and zeros). A circuit, known as a transmitter in the sending device, converts each word into a sequence of electrical pulses, and transmits the sequence of pulses based on a clock signal to the receiving device. The receiving device includes a receiver circuit that first determines the timing of the pulses and then identifies each of the pulses in the received signal as a one or zero, enabling it to reconstruct the original set of digital words.
A key part of both the transmitter and the receiver is a clock-generation circuit that generates several matched timing, or clock, signals that oscillate back and forth between a high and a low voltage level at the same frequency. Although the matched clock signals have the same frequency, they are delayed relative to each other so that each signal reaches the high (or low) voltage level at a slightly different time. For example, with three clock signals, the first would reach the high voltage level, then after a delay, the second would reach the high voltage level, and finally after another delay, the third would reach the high voltage level. This same pattern repeats as each clock signal transitions from the high voltage level to the low voltage level, with each signal reaching this low level in sequence, and then moving back to the high voltage level - - - like a series of three traffic lights changing from red to green and back to red, one after the other.
To promote accurate communications between the transmitter and receiver, the delay between the first and second clock signals and the delay between the second and third clocks signals are ideally the same. In the transmitter, the same delay ensures accurate conversion of parallel data to serial data, and in the receiver, the same delay ensures accurate interpretation of a received signal pulse as a one or a zero. However, in practice, there are factors that prevent the delays (or phase relationships) between these clock signals from being the samexe2x80x94in other words, from being perfectly matched.
One of these factors is that each clock signal is conducted to different components of the transmitter and receiver circuitry, and each component has unique electrical traits, such as resistance and capacitance, that affect when each clock signal reaches the high or low voltage level within the component. Voltages within components that have high resistance and capacitance take longer to transition from high to low and low to high than voltages in components that have low resistance and capacitance (assuming all other factors are equal.) As a result, the delay between the clock signals sent to these components vary from what was initially desired. This phenomenon of variant phase relationships among the supposedly matched clock signals causes xe2x80x9cjitterxe2x80x9d in transmitted data and reduced jitter tolerance in the receiver.
In the past, the jitter and jitter-tolerance reduction stemming from component mismatches (also known as load mismatches) was of less practical significance, because the frequencies of operation were lower and afforded sampling circuits and other types of communications circuits that have a relatively large margin for jitter-related timing errors. However, more recently, the present inventors have recognized that the demands to transfer more data in less time between electronic devices have driven data-transmission frequencies into the gigahertz ranges (a gigahertz is one billion oscillations per second) and thus reduced the margin for these timing errors. At these higher frequencies, any appreciable jitter or jitter-tolerance reduction reduces the accuracy of communications between the transmitter and receiver.
Accordingly, the present inventors have recognized a need for improving the matching of clock signals and thus reducing jitter in transmitted data and improving the jitter tolerance of receivers.
To address these and other needs, the present inventors devised a unique clock distribution method which improves clock matching and thus can be used in transmitters to reduce jitter and in receivers to improve jitter tolerance. The exemplary scheme entails generating a base set of matched clock signals, deriving at least two separate sets of matched clock signals from the base set, and distributing the separate sets of matched clock signals to respective portions of a circuit. One portion of the circuit has a set of substantially matched subcircuits (components with matched electrical characteristics), each one coupled to receive one of the matched clock signals, and the other portion has no load-matching requirements. The clock signals coupled to the portion having matched loads are more closely matched than those that are coupled to the other portion of the circuit. The portion having matched loads may be used to produce data signals having less jitter, or to process data signals having a higher degree of jitter, thereby improving overall jitter performance of the circuit.
For example, one receiver incorporating the exemplary scheme produces two substantially identical sets of matched clock signals. One of the sets of matched clock signals drives the samplers in a bank of matched phase detectors, and the other set drives the latches and logic gates in the phase detectors. The load characteristics of the latches and logic gates differ significantly from each other and thus cause a certain amount of mismatch in the clock signals driving them, whereas the load characteristics of the samplers across the bank of phase detectors are highly matched (according to fabrication tolerances) and thus preserve matching of their corresponding clock signals. In effect, the clock signals driving the matched samplers are isolated from the mismatched load of the latches and the logic gates. Since the samplers are sensitive to clock matching, and the latch and logic gates are less sensitive, this isolation ultimately allows the receiver to accurately process signals having a greater degree of jitter.
One exemplary transmitter incorporating the scheme produces two substantially identically sets of matched clock signals and includes a parallel-to-serial converter. One of the sets of matched clock signals drives shift registers that can use less stringently matched clock signals, and the other drives multiplexers that require well-matched clock signals. This exemplary transmitter ultimately transmits data signals that have less jitter than conventional designs, and thus facilitates accurate communications.
Other aspects of the invention include transceivers that incorporate the exemplary receiver and/or transmitter. Additional aspects of the invention include related methods and systems. For example, some systems combine one or more of these components with programmable logic devices.